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[Other resourceldpc_decoder_802_3an

Description: 802.3an ldpc码编码、译码设计,使用VERILOG hdl语言编写,包括测试代码,
Platform: | Size: 788866 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilogldpc_decoder_802_3an

Description: 802.3an ldpc码编码、译码设计,使用VERILOG hdl语言编写,包括测试代码,-802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,
Platform: | Size: 788480 | Author: 聂样 | Hits:

[Communication-Mobileldpc

Description: 最近在做毕设,ldpc码的编解码实现,这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
Platform: | Size: 9216 | Author: fly | Hits:

[VHDL-FPGA-VerilogRealization_of_FPGA_for_LDPC_encoding

Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码,它的直接编码运算量较大,通常具有码长的二次方复杂度.为此,利用有效的校验矩阵,来降低编码的复杂度,同时研究利用大规模集成电路实现LDPC码的编码.在ISE 8.2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程,为LDPC码的硬件实现和实际应用提供了依据-Abstract:Low.density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit.For LDPC cod e,the computational overhead for direct encoding operations is large,as the complexity of encod ing is the square of the length of codeword.Hence,this paper reduces the complexity of coding by using effective parity—check matrix,and realizes the encoding device for LDPC code by use of large·scale integrated circuits.The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8.2 software platform ,providing a feasible basis for hardware implementation an d practical application of LDPC code.
Platform: | Size: 165888 | Author: 秦小星 | Hits:

[Software Engineeringldpc

Description: 移动通信技术中信道编码的LDPC码的Verilog hdl 实现-Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
Platform: | Size: 2048 | Author: 杜欧鸥 | Hits:

[Software EngineeringMS_LDPC

Description: 移动通信技术中信道编码的LDPC码的译码Verilog hdl 实现-Decoding Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
Platform: | Size: 1024 | Author: 杜欧鸥 | Hits:

[Software Engineeringvnp

Description: 移动通信技术中信道编码的LDPC码的VNP的Verilog hdl 实现-Channel coding of mobile communication technology LDPC code VNP realization of Verilog hdl
Platform: | Size: 1024 | Author: 杜欧鸥 | Hits:

[3G developXOR_tree

Description: This source code is a check node unit for LDPC decoder. The language is Verilog HDL.
Platform: | Size: 4321280 | Author: Lee Jeahack | Hits:

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